YouTube 頻道

UCIe Consortium

@UCIe Consortium · —

The UCIe Consortium is an industry consortium dedicated to advancing UCIe™ (Universal Chiplet Interconnect Express™) technology, an open industry standard that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. UCIe Consortium is led by key industry leaders Advanced Semiconductor Engineering, Inc. (ASE), Alibaba, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, NVIDIA, Qualcomm Incorporated, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company. For more information, visit www.UCIexpress.org.

查看 YouTube 頻道

PERFORMANCE SNAPSHOT

核心表現

公開快照中的近期可用數據

資料維度載入中

訂閱數2,040

觀看數79,046

影片數16

CONTENT INTELLIGENCE

近期內容表現

以同一觀看單位比較最多三支公開影片

3 支可比較內容

Driving the Future of Automotive Compute with UCIeYouTube 影片

211

The Growing Chiplet Ecosystem: Collaboration, Innovation, and the Next Wave of UCIe™ AdoptionYouTube 影片

767

Introducing the UCIe™ 3.0 Specification: Continued Innovations in the Open Chiplet EcosystemYouTube 影片

2,989

近期影片

Driving the Future of Automotive Compute with UCIe

As vehicles become increasingly defined by their compute architecture, Advanced Driver-Assistance Systems (ADAS), AI-driven workloads, centralized compute, and zonal vehicle designs are placing new demands on automotive silicon. Meeting these requirements while balancing power efficiency, reliability, functional safety, cost, and long product lifecycles is driving the industry toward more modular and scalable chiplet-based architectures. Watch the webinar featuring members of the UCIe Consortium's Automotive Working Group, including experts from Cadence and AMD, as they explore how UCIe is enabling next-generation automotive compute platforms through open die-to-die interconnect standards. The discussion highlights how chiplet-based architectures can improve interoperability, scalability, and ecosystem collaboration to address the evolving needs of automotive semiconductor design. Viewers will also gain insight into the UCIe Consortium's Automotive Working Group and its efforts to advance automotive-specific requirements for interoperability, reliability, and scalable integration as vehicle electronics continue to grow in complexity.

觀看 211按讚 3留言 0

觀看影片 ↗

The Growing Chiplet Ecosystem: Collaboration, Innovation, and the Next Wave of UCIe™ Adoption

Moderator: Brian Rea (UCIe Marketing Workgroup Co-Chair; Intel) Panelists: Archana Cheruliyil (Alphawave Semi), Vishal Chandrasekar (Ayar Labs), Mayank Bhatnagar (Cadence), Justin Bunnell (Siemens), and Manuel Mota (Synopsys) Chiplets are reshaping how advanced systems are designed, delivering new levels of performance, scalability, and flexibility. At the heart of this transformation, the UCIe™ (Universal Chiplet Interconnect Express™) specification is growing into the de facto standard that unites our ecosystem around a common, interoperable foundation. In this webinar, UCIe Consortium members will discuss how UCIe 3.0’s expanding set of features is supporting a broader range of chiplet use cases and real-world implementations. Hear how companies are collaborating to advance adoption, streamline integration, and enable next-generation applications, from high-bandwidth memory to optical interconnects. The panelists will share insights into real-world collaborations, growing market momentum, and how the community is working together to make chiplet integration more accessible, flexible, and future-ready. Whether you’re an engineer, technologist, or strategist following the evolution of open standards, this session will offer a real-time view into how UCIe is shaping the path forward for the chiplet ecosystem. Join us for an inside look at active UCIe chiplet member implementations and how you can get involved in chiplet collaboration.

觀看 767按讚 11留言 0

觀看影片 ↗

Introducing the UCIe™ 3.0 Specification: Continued Innovations in the Open Chiplet Ecosystem

The UCIe™ 3.0 Specification: Doubling Bandwidth, New Use Cases, and Enhanced Manageability for Scalable SiP Architectures Aired: September 18, 2025 at 9:00 a.m. PT The UCIe™ (Universal Chiplet Interconnect Express™) 3.0 specification was released in August 2025, doubling the data rates, delivering 48/64 GT/s speeds for UCIe-S and UCIe-A, to power next-gen multi-chip systems for evolving use cases, such as AI which continue to demand ever increasing bandwidth density, while maintaining low power. This webinar will delve into the new features in the UCIe 3.0 specification including improvements to bandwidth density, power efficiency, enhanced manageability, and expanded design flexibility for scalable SiP architectures. The webinar will also cover new enhancements introduce in the UCIe 3.0 specification, such as runtime recalibration for improved power efficiency and extended sideband reach that supports more flexible multi-chip configurations. Additionally, the webinar will explore new manageability features like early firmware download and priority sideband packets increase system responsiveness and reliability. Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman, and Intel Senior Fellow and co-GM Memory and I/O Technologies, Intel Corporation

觀看 2,989按讚 33留言 0

觀看影片 ↗

A Deep Dive into UCIe-3D

With increasing demands for higher performance, bandwidth density, and power efficiency the industry is rapidly adopting 2.5D and 3D packaging technologies to address these challenges. This shift highlights the pressing need for a unified industry ecosystem standard—one that provides a standardized architecture for streamlined manageability and addresses the unique design complexities of advanced packaging. The UCIe 2.0 specification supports 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. Join us in this webinar as we dive into the benefits of UCIe-3D including its hybrid bonding optimization, flexible bump pitch adaptability, and the scalability needed to drive the next wave of chiplet and packaging innovations. Presenter: Zuoguo (Joe) Wu, UCIe Consortium Electrical Working Group Co-Chair and Sr Principal Engineer at Intel

觀看 3,667按讚 59留言 2

觀看影片 ↗

Introducing the UCIe 2.0 Specification Supporting 3D Packaging and Manageability System Architecture

The UCIe™ (Universal Chiplet Interconnect Express™) 2.0 Specification was released in August 2024, adding support for a standardized system architecture for manageability and holistically addresses the design challenges for testability, manageability, and debug (DFx) for the SIP lifecycle across multiple chiplets – from sort to management in the field. The webinar explores the new features in the UCIe 2.0 specification including support for 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. The webinar also introduces optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions. It also enables vendor agnostic chiplet interoperability across a flexible and unified approach to SIP management and DFx operations. Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman, and Intel Senior Fellow and co-GM Memory and I/O Technologies, Intel Corporation

觀看 5,384按讚 49留言 1

觀看影片 ↗

Exploring the Advancement of Chiplet Technology and the Ecosystem

Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller, modular chiplets, designed for a specific function, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements. UCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. This webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI, ML, aerospace, and automotive. Moderator: Brian Rea (UCIe Marketing Workgroup Co-Chair, Intel) Panelists: Ericles Rodrigues Sousa (UCIe Automotive Workgroup Co-Chair, Cadence Design Systems), Hee-Soo Lee (Keysight Technolgies), and Saman Sadr (Neuron IP)

觀看 1,955按讚 15留言 0

觀看影片 ↗

資料擷取時間：2026-09-07T08:07:59.000000Z

公開欄位僅來自目前發布的 YouTube 頻道快照；缺值以「—」呈現。